1. Field of the Invention
The invention relates to a data packet transporting method. Particularly, the invention relates to a method for transporting data with embedded clock.
2. Description of Related Art
Data transmission is indispensable in operations of electronic products. Regarding a digital display panel, for example, a thin-film transistor liquid crystal display (TFT-LCD) panel, a required data rate of a data transmission interface (reduced swing differential signalling (RSDS) or mini-low-voltage differential signalling (LVDS)) commonly used by a timing controller (TCON) and a source driver of the TFT-LCD panel is far beyond a load level of the current data transmission interface due to various new applications such as solution of motion blur under 120 Hz or three-dimensional (3D) display under 240 Hz, or demand for a slim border. A direct solution is to increase the number of channels in the interface. FIG. 1 is a schematic diagram of a conventional data transmission structure. Referring to FIG. 1, a TCON 100 transmits signals to each of source drivers (D-IC) 106 in a parallel manner through a bus containing data lines 104 and a clock line 102. As a result, electromagnetic interference (EMI) is aggravated, and the demand for slim border cannot be achieved, and even the cost is increased. Therefore, to modify a transmission technique of the interface to increase the data rate of a single channel is obviously a more practical solution.
In a commonly used high-speed serial interface, a clock embedded method is generally used to remove a skew of a clock channel and a data channel, and a point-to-point bus structure is used, as that shown in FIG. 2. FIG. 2 is a schematic diagram of a conventional point-to-point data transmission structure. Referring to FIG. 2, a TCON 120 is connected to each of the source drivers (D-IC) 122 in the point-to-point manner, where a clock signal is embedded in transmitted data, so that it is unnecessary to use an extra clock line. Such method can reduce loss caused by wiring on a substrate due to a matching problem. Regarding the clock embedded technique, a coding method having a direct current (DC) balance and a run length limited characteristics is used to code original data, and such two characteristics facilitate a receiver to easily extract a correct clock phase and frequency, so as to obtain the correct original data. For example, 8b/10b, 4b/5b, . . . , etc. are all belong to such coding method. A main principle thereof is that a coded data string has almost the same appearance rate (the DC balance) of 0 and 1, and the number of consecutive appearance of 0 or 1 is ensured to be smaller than a fixed value (the run length limited), though a certain amount of redundancy has to be added, for example, a coding efficiency (CE) of 8b/10b is 0.8, which represents that every 10 coded data bits only includes the original data of 8 bits, i.e. 2 bits are redundancy or overhead, the clock embedded method using the coding manner has been widely used in various applications.
FIG. 3 is a schematic diagram of a circuit structure for transmitting data by using a conventional 8b/10b coding mechanism. Referring to FIG. 3, parallel data is received by an 8b/10b encoder 130 for an 8b/10b coding. A parallel to serial converter 132 converts coded parallel data into serial data, and the serial data is transmitted through a transmitter 134. FIG. 4 is a schematic diagram of a circuit structure for receiving data by using the conventional 8b/10b coding mechanism. Referring to FIG. 4, a receiver 136 receives the 8b/10b-coded data, and a serial to parallel converter 138 is first used to convert the serial data into parallel data, and the conversion process is implemented in collaboration with operations of a phase/frequency comparator 142, a low pass filter (LPF) 144 and a voltage-controlled oscillator (VCO) 146. The converted parallel data is then decoded by an 8b/10b decoder 140 to obtain the original parallel data.
Although the clock embedded method using the coding manner can achieve a higher data rate, hardware cost and power consumption thereof are obviously increased.